Design of Control Unit

The control unit is a vital part of a computer’s CPU that generates the necessary timing and control signals to manage the operations of the entire system. It coordinates with the Arithmetic Logic Unit (ALU) and main memory, controlling the flow of data between the processor, memory, and peripherals. Additionally, it directs the ALU on which operation to perform on the data.

The control unit can be designed using two primary methods:

  1. Hardwired Control
  2. Microprogrammed Control

1. Block Diagram Hardwired Control:

Block Diagram Hardwired Control unit:
Block Diagram Hardwired Control:
  • The Hardwired Control organization implements control logic with gates, flip-flops, decoders, and other digital circuits.
  • The block diagram of a Hardwired Control organization includes the following components:
  • Two decoders
  • A sequence counter
  • Several logic gates
  • An instruction fetched from the memory unit is placed in the Instruction Register (IR).
  • The Instruction Register (IR) contains several parts:
    • Bits 0 through 11 represent the operand.
    • Bits 12 through 14 represent the operation code (Opcode).
    • Bit 15 is used for the mode.
  • The operation code (bits 12-14) is decoded by a 3 x 8 decoder.
  • The outputs of the decoder are labeled D0 to D7.
  • The mode bit (bit 15) is transferred to a flip-flop, labeled I.
  • The operand (bits 0-11) is applied to the control logic gates.
  • The Sequence Counter (SC) can count in binary from 0 to 15.

 

2. Microprogrammed Control Unit:

  • The Micro-programmed Control organization is based on a programming technique where control is managed through micro-programs. These micro-programs consist of micro-instructions that define the control signals for each operation.
  • A Block diagram of the Micro-programmed Control organization is shown below.
Micro-programmed-Control
Micro-programmed-Control

A Block diagram of the Micro-programmed Control organization typically includes the following components:

  • The Control Memory Address Register (CMAR) specifies the address of the current micro-instruction to be fetched from the control memory.
  • The Control Memory is usually implemented as a ROM (Read-Only Memory), where all the control information is permanently stored.
  • The Control Register holds the micro-instruction that has been fetched from memory.
  • Each micro-instruction contains a control word, which defines one or more micro-operations that the data processor should perform.
  • While the micro-operations are being carried out, the next address for the following micro-instruction is computed by the Next Address Generator circuit. This address is then transferred into the Control Memory Address Register to fetch the next micro-instruction.
  • The Next Address Generator is sometimes called a Micro-program Sequencer, as it determines the sequence of addresses to be read from the control memory.

Advantages

  • It is less complex to design because micro-programs are implemented using software routines.
  • It is more flexible because design modification, correction, and enhancement are straightforward.
  • Errors can easily be removed.

Disadvantages

  • This Technology is slower than the hardwired control unit because the time required to access the micro-instructions from control memory is larger.
  • It is more expensive than hardwired due to the use of ROM.
  • Required more Chip area as compared to hardwire

 

Arithmetic Logic Unit

The ALU is also called the Integer Unit (IU). It’s a part of the CPU that does all the calculations needed by the computer. Most of these calculations are related to logic operations. The design of the ALU affects how powerful the CPU is. A more powerful ALU can make the CPU faster, but it also uses more energy and produces more heat. Because of this, there needs to be a balance between the power of the ALU and the cost, energy use, and heat it generates. This is why faster CPUs are more expensive, use more power, and create more heat.

The different tasks carried out by the ALU can be grouped into the following categories:

  1. Logical operations: These include tasks like AND, OR, NOT, XOR, NOR, and NAND.

  2. Bit-shifting operations: This involves moving the positions of bits to the left or right. Shifting bits left is like multiplying by 2, and shifting them right is like dividing by 2.

  3. Arithmetic operations: This includes simple operations like adding and subtracting bits. While multiplication and division are also possible, they are more complicated and expensive to do. Instead, multiplication can be done through repeated addition, and division can be done using repeated subtraction.


 

Registers

  • A register is a very fast memory used by the CPU to store and transfer data and instructions that are needed immediately.
  • A register can be thought of as a group of flip-flops, with each flip-flop storing one bit of information.
  • A register with n flip-flops can store n bits of binary data.
  • The flip-flops hold the binary data, while gates control the flow of information, deciding when and how data is transferred into the register.
  • There are different types of registers available. A basic register only contains flip-flops without any external gates.
  • When new data is added to a register, this process is called loading the register.
    4 bit Resister
    4-bit Resister
  • The above figure shows a register constructed with four D-type flip-flops and a common clock pulse-input.
  • The clock pulse-input, CP, enables all flip-flops so that the information presently available at the four inputs can be transferred into the four-bit register.

 

 The list of some of the most common registers

RegisterSymbolNumber of bitsFunction
Data registerDR16Holds memory operand
Address registerAR12Holds address for the memory
AccumulatorAC16Processor register
Instruction registerIR16Holds instruction code
Program counterPC12Holds address of the instruction
Temporary registerTR16Holds temporary data
Input registerINPR8Carries input character
Output registerOUTR8Carries output character

Bus Architecture:

A bus is a collection of wires, chips, and slots inside the computer through which data are transmitted from one part of the computer to another from peripheral devices. It is also called a pathway in the computer on which data travels. It is a set of parallel distinct wires, serving different purposes, which allow devices attached to it to communicate with the CPU.

The block diagram bus architecture is shown in the below diagram.  

Figure: Bus Architecture
Figure: Bus Architecture

Functions of a Bus:

  1. It helps send information from one part of the computer to another.
  2. It carries data, addresses, and control signals.
  3. It allows devices to communicate with each other through the CPU.

There are three main parts of a bus:

1. Control Bus:

  • The control bus carries “control signals,” which are used to manage and organize the activities of the computer. These signals are sent by the control unit in the CPU.
  • For example, the control bus helps tell the CPU whether it should be reading or writing data or if it needs to reset something.
  • The control bus uses individual lines (wires) to send specific commands to the CPU, like “read data” or “write data.”

2. Address Bus:

  • The address bus is responsible for carrying memory addresses. Think of it like an address book – it helps the CPU know where to find or send data.
  • It connects the CPU to memory and other devices and carries the “address” where the data should go or come from. This address is a unique number that identifies where the data is stored.
  • The address bus only moves in one direction, from the CPU to other devices, and helps the CPU know which memory location or device it’s working with.

Addressing Modes:

  • In computer architecture, addressing modes define how the CPU identifies the location of an operand (the data that an instruction operates on). Based on the instruction, they determine how the operand is accessed or where it is located.
  • Here are the main types of addressing modes are numerining below.
  1. Implicit
  2. Immediate
  3. Direct
  4. Indirect
  5. Register
  6. Register Indirect
  7. Displacement
  8. Relative
  9. Base register
  10. Indexing
  11. Stack

2. Immediate address mode: In the immediate addressing mode, the instruction contains two fields. One is for the opcode, and another field contains the operand itself. That means in this addressing mode, there is no need to go anywhere to access the operand because the instruction itself contains the operand. This is known as the immediate addressing mode.

Immediate address mode

3.Direct addressing mode :

  • In the direct addressing mode, the instruction will have two parts. One part will contain the opcode, and another part will contain the address of the memory location where the operand can be found.
  • Here, A is the address of the operand. That means that at the Ath location in the memory, the operand can be found
    Direct Addressing Mode
    Direct Addressing Mode

    4. Indirect addressing mode :

  • The indirect addressing mode contains the opcode and address fields. But unlike the direct addressing mode, it doesn’t contain the address of the operand but contains the address of a memory location in which the actual address of the operand can be found.

Indirect addressing mode
Indirect addressing mode

Here, A contains the address of the location B in memory and B contains the actual address of the operand in memory.

5. Register addressing mode:

  • In the case of the register addressing mode, the instruction will have the opcode and a register number. Depending upon the register number, one of the registers will be selected from the available sets of registers by default automatically.
  • The unique identification of the register can be done by the register number, which is mentioned in the instructions. In that register, the operand can be found.

6 . Register indirect addressing mode :

  •  In the register indirect addressing mode, the instruction will contain the opcode as well as a register number. Depending upon the register number mentioned in the instruction, the corresponding register will be accessed from the set of registers. But here the register doesn’t contain the operand but will contain the address of the operand in the memory at where the operand can be found
Register indirect addressing mode
Register indirect addressing mode

7. Displacement addressing mode :

In the displacement addressing mode, the instruction has three parts: one for the operation code (opcode), one for the register number, and one for an absolute address.

First, based on the register number, the specific register is chosen from a set of registers. Then, the value in that register is added to the absolute address. The result is the actual physical address in memory where the operand (data) is located.

Displacement addressing mode
Displacement addressing mode

In computer architecture, displacement addressing mode can be divided into three types:

  1. Relative Addressing Mode
  2. Base Register Addressing Mode
  3. Indexing Addressing Mode

1. Relative Addressing Mode:

In relative addressing mode, the register used is the program counter (PC). This means the address is calculated relative to the current position in the program.

2. Base Register Addressing Mode:

In base addressing mode, the register holds the base address, and the absolute field contains the offset or displacement from this base address. By adding both the base address and the offset, you get the actual physical address of the operand in memory.

For example, if the base address is 3000 and the offset is 20, the result would be 3020, which would be the address of the operand.

3. Indexing Addressing Mode:

In indexing mode, the absolute field holds the starting address of the memory block, while the register contains the index value. Adding both gives the actual physical address of the operand.


Stack Addressing Mode:

In stack addressing mode, the instruction always refers to the topmost data as the operand.

  • If the instruction is unary, it uses the topmost data from the stack.
  • If the instruction is binary, it uses the top two data elements from the stack as operands.
Stack addressing mode
Stack addressing mode

Types of Processors

1. RISC Processors (Reduced Instruction Set Computer):

  • RISC processors are designed to execute instructions with fewer steps and simpler hardware. In this design, the control unit of the processor generates control signals to execute each instruction using separate electronic circuitry. This approach is known as the hard-wired or hardware approach because it relies on fixed logic circuits rather than using software instructions.

Examples of RISC processors:

  • DEC’s Alpha 21064, 21164, and 21264 processors
  • SUN’s SPARC and ULTRA SPARC processors
  • PowerPC processors

2. CISC Processors (Complex Instruction Set Computer):

  • CISC processors, on the other hand, use a more complex control unit that includes microelectronic circuitry. Each piece of circuitry is activated by a microcode to generate the necessary control signals. This approach is known as the software approach because it relies on microprogramming to control the processor.

Examples of CISC processors:

  • Intel 386, 486
  • Pentium series (Pentium Pro, Pentium, Pentium II, Pentium III, Pentium 4)
  • Motorola’s 68000, 68020, 68030, 68040 series

 

Difference between RISC and CISC:

FeatureRISC (Reduced Instruction Set Computer)CISC (Complex Instruction Set Computer)
Instruction SetSimple and small number of instructionsComplex with many instructions
Instruction LengthFixed instruction lengthVariable instruction length
Execution TimeFaster execution (more instructions per task)Slower execution due to more complex instructions
Control UnitHard-wired control signalsUses microcode to generate control signals
ComplexitySimpler hardware designMore complex hardware design
Memory UsageTypically requires more instructions for complex tasksFewer instructions due to complex instructions
ExamplesPowerPC, SPARC, ARMIntel Pentium, Motorola 68000

 

Frequently Asked Questions.

 

1. What is the difference between RISC and CISC processors?

  • RISC (Reduced Instruction Set Computer) uses simpler and fewer instructions, each of which is executed in a single cycle. The design focuses on simplicity, with a fixed instruction length and hard-wired control logic.
  • CISC (Complex Instruction Set Computer) uses more complex instructions, which can take multiple cycles to execute. The design is based on a wider variety of instructions and relies on microcode to control the execution of complex tasks.

2. Which is better: RISC or CISC?

The choice between RISC and CISC depends on the application. RISC is typically faster because it uses simpler instructions that can be executed more quickly, making it ideal for applications requiring high performance. CISC, however, may be more efficient in terms of the number of instructions needed for certain tasks since each instruction can perform multiple operations. CISC processors are often used in general-purpose computing.

3. Which processors use RISC?

Some well-known processors that use RISC architecture include:

  • PowerPC processors
  • SPARC and UltraSPARC processors by SUN Microsystems
  • ARM processors (used in smartphones and tablets)

4. Which processors use CISC?

Processors that use CISC architecture include:

  • Intel Pentium series (e.g., Pentium Pro, Pentium III, Pentium 4)
  • Intel 386, 486 processors
  • Motorola 68000 series

5. What are the advantages of RISC?

  • Faster execution: Since RISC uses simpler instructions that take fewer cycles, it can execute tasks more quickly.
  • Simpler design: RISC processors typically have a simpler architecture, which makes them easier to design, maintain, and optimize.
  • Lower power consumption: RISC chips usually consume less power due to their simpler operations.

6. What are the advantages of CISC?

  • Complex instructions: CISC processors can perform more complex operations with fewer instructions, which may reduce the overall program size.
  • Efficiency in certain tasks: CISC can be more efficient for certain types of applications that require complex operations in a single instruction.

7. Can RISC and CISC coexist?

Yes, many modern processors combine aspects of both RISC and CISC. For example, Intel’s x86 architecture (which is CISC) has incorporated elements of RISC to improve performance. These hybrid processors try to balance the simplicity of RISC with the complexity of CISC.

8. Why is RISC considered faster than CISC?

RISC processors can execute each instruction in a single cycle, making them faster at executing many simple instructions. CISC processors, with their complex instructions, often require multiple cycles to execute a single instruction, which can slow down performance.

9. Do RISC processors have fewer instructions?

Yes, RISC processors use a smaller and simpler set of instructions compared to CISC processors. This means each RISC instruction typically performs a single operation, making it faster and more efficient at executing basic tasks. However, more instructions may be needed for complex operations.

10. Is RISC used in mobile devices?

Yes, ARM processors, which are based on RISC architecture, are widely used in mobile devices like smartphones and tablets due to their efficient performance and low power consumption.

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